Combined Transistor Sizing with Bu er Insertion for Timing Optimization

This paper presents strategies to insert bu ers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeo s. The delay model incorporates placement-based information and the e ect of input slew rates on gate delays. The results obtained by using the new method are signi cantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.